The present invention relates to an on-line self-calibration scheme of a digital compensation filter for performing digital compensation filtering on baseband data to be utilized by a phase locked loop (PLL) within a transmitter, and more particularly, to a method for tuning a digital compensation filter within a transmitter, and to an associated digital compensation filter and an associated calibration circuit.
Digital intensive RF design is of great research interest recently, where RF circuit requirements could be relaxed because of the possibility of digitally repairing RF impairments, and designs could be migrated to different technology node or foundry much more effortlessly. One exemplary application is the direct-frequency-modulated (DFM) PLL, where the baseband signal is pre-emphasized digitally to compensate for PLL low pass response. The PLL's loop bandwidth can therefore be optimized for noise filtering while high data rate modulation is still possible. However, problems such as mismatch between PLL loop bandwidth and the conventional digital pre-emphasis filter will result in significant transmission signal quality degradation. Precise control for loop parameters such as voltage-controlled oscillator (VCO) gain and loop gain and improving robustness against process-voltage-temperature (PVT) variations are keys for mass production of the DFM PLLs. According to the related art, the so-called all-digital PLL (ADPLL) is one candidate for implementing the DFM PLLs. However, it still suffers from the limitations of wide tracking range and its complicated design procedure. Moreover, temperature to digital converter (TDC) resolution and digital controlled oscillator (DCO) gain are unfortunately both PVT sensitive parameters. Thus, a novel method is required for providing precise loop parameter control and improving robustness against PVT variations.